Pixel structure and method for fabricating the same

ABSTRACT

A pixel structure is disclosed. The pixel structure includes a substrate, a first data line having at least one end formed on the substrate, a first insulation layer overlying the first data line and exposing a part of the end of the first data line, a shielding electrode disposed on the first insulation layer and overlapped with the first data line, a second data line formed on the first insulation layer and electrically connected to the exposed end of the first data line, a second insulation layer overlying the shielding electrode and the second data line, and a pixel electrode formed on the second insulation layer and overlapped with the shielding electrode. The invention also provides a method for fabricating the pixel structure.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor structure, and in particular toa pixel structure and a method for fabricating the same.

2. Description of the Related Art

In liquid crystal display fabrication, the aperture ratio of pixelsaffects utilization of backlight and panel brightness. The apertureratio is determined by the interval between the conductive electrode anddata line. However, the capacitance between pixel and data line (Cpd)may increase when the interval is small, resulting in crosstalk.

To reduce capacitance between pixel and data line (Cpd), methods caninclude, for example, increasing storage capacitance to reduce the ratioof Cpd in total capacitance of a sub-pixel, disposing a stable electricshield between the pixel electrode and data line to reduce the parasiticcapacitance therebetween, and utilizing an organic low-k insulation film(K=2.7˜3.5) formed by the photo-imaged or spin on glass (SOG) methodsprovided by Optical Imaging Systems (OIS) to reduce the capacitancebetween pixel and data line.

However, increasing the area of the storage capacitor may reduce theaperture ratio. Also, the organic low-k insulation film with strongwater adsorption, yellowing, and low interface adhesion may affect yieldand throughput.

FIG. 1A is a top view of a conventional pixel structure. FIG. 1B is across sectional view taken along A-B line of FIG. 1A. A pixel structure1 comprises two insulation layers such as a gate insulation layer 2 anda passivation layer 3, and two metal layers. One of the metal layers isfabricated to form a gate line 4 and a common line 5. Another metallayer is fabricated to form a data line 6 and a source/drain 7. In thestructure, the parasitic capacitance between the data line 6 and thepixel electrode 8 can be reduced due to a proper interval therebetween.A large black matrix, however, is required to sufficiently shield thelight leak region, thus decreasing the aperture ratio.

BRIEF SUMMARY OF THE INVENTION

In one aspect, the invention provides a pixel structure comprising asubstrate, a first data line having at least one end formed on thesubstrate, a first insulation layer overlying the first data line andexposing a part of the end of the first data line, a shielding electrodedisposed on the first insulation layer and overlapped with the firstdata line, a second data line formed on the first insulation layer andelectrically connected to the exposed end of the first data line, asecond insulation layer overlying the shielding electrode and the seconddata line, and a pixel electrode formed on the second insulation layerand overlapped with the shielding electrode.

In another aspect, the invention also provides a method for fabricatinga pixel structure, in which a substrate is provided. A scan lineextending in a first direction and a first data line extending in asecond direction are formed on the substrate. A first insulation layeris formed on the substrate, overlying the scan line and the first dataline. A patterned semiconductor layer is formed on the first insulationlayer. A shielding electrode and a second data line are formed on thefirst insulation layer and a source and a drain are formed on thepatterned semiconductor layer, wherein the shielding electrode overlapsthe first data line and the second data line is electrically connectedto the end of the first data line. A second insulation layer is formedover the shielding electrode, the second data line, the source, and thedrain. An opening is formed to expose the drain. A pixel electrode isformed on the second insulation layer, wherein the pixel electrode iselectrically connected to the drain through the opening and overlaps theshielding electrode.

A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequentdetailed description and examples with references made to theaccompanying drawing, wherein:

FIG. 1A is a top view of a conventional pixel structure.

FIG. 1B is a cross sectional view taken along A-B line of FIG. 1A.

FIG. 2A is a top view of a pixel structure of the invention.

FIG. 2B is a cross sectional view taken along A-A′, B-B′, and C-C′ linesof FIG. 2A.

FIGS. 3A˜3G are cross sectional views illustrating a method forfabricating a pixel structure according to one embodiment of theinvention.

FIGS. 4A˜4F are cross sectional views illustrating a method forfabricating a pixel structure according to another embodiment of theinvention.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carryingout the invention. This description is made for the purpose ofillustrating the general principles of the invention and should not betaken in a limiting sense. The scope of the invention is best determinedby reference to the appended claims.

FIG. 2A is a top view of a pixel structure of the invention. FIG. 2B isa cross sectional view taken along A-A′, B-B′, and C-C′ lines of FIG.2A. The pixel structure 10 comprises a substrate 12, a first data line14, a first insulation layer 16, a shielding electrode 18, a second dataline 20, a second insulation layer 22, and a pixel electrode 24.

The first data line 14, having at least one end 26, is formed on thesubstrate 12. The first insulation layer 16 overlies the substrate 12and the first data line 14 to expose a part of the end 26 thereof. Theshielding electrode 18 is disposed on the first insulation layer 16 andoverlaps the first data line 14. The second data line 20 is formed onthe first insulation layer 16 and electrically connected to the exposedend 26 of the first data line 14. Specifically, the first data line 14and the second data line 20 form one data line. The second insulationlayer 22 overlies the shielding electrode 18 and the second data line20. The pixel electrode 24 is formed on the second insulation layer 22and overlaps a part of the shielding electrode 18.

Referring to FIG. 2A, the pixel structure 10 further comprises a scanline 28 intersecting the second data line 20 formed on the substrate 12.The pixel structure 10 further comprises a thin film transistor 36having a gate 30 electrically connected to the scan line 28, a source 32electrically connected to the second data line 20, and a drain 34electrically connected to the pixel electrode 24. The shieldingelectrode 18 exhibits a network comprising a first sub-shieldingelectrode 18′ extending along a first direction and across the firstdata line 14, and a second sub-shielding electrode 18″ extending along asecond direction across the scan line 28. A part of the secondsub-shielding electrode 18″ in the second direction overlaps with thefirst data line 14. Additionally, the scan line 28 and the first dataline 14 are composed of the same metal layer. The shielding electrode18, the second data line 20, the source 32, and the drain 34 arecomposed of the same metal layer.

The two-dimensional network structure of the shielding electrodeprovides a uniform electric potential and avoids weak lines caused bybreak or short of conventional one-dimension shielding electrode.

The shielding electrode 18, overlapping the first data line 14, islocated between the pixel electrode 24 and the first data line 14 andshields the electric field produced from the first data line 14, asshown in FIG. 2B. A storage capacitor 38 is formed between the shieldingelectrode 18 and the pixel electrode 24, as shown in FIG. 2A & FIG. 2B.The storage capacitor 38 is formed between the pixel electrode 24 andthe first sub-shielding electrode 18′ and the second sub-shieldingelectrode 18″.

A conventional structure including a shielding electrode, a pixelelectrode and a data line sandwiched between the shielding electrode andthe pixel electrode is replaced with the structure disclosed, whichcomprises a data line, a pixel electrode and a shielding electrodesandwiched between the data line and the pixel electrode, withoutadditional metal conductive films and insulation layers, reducing costand increasing throughput. Additionally, the stray capacitance producedform the electric field of the data line is reduced and the storagecapacitance is increased, acquiring an optimal quality of pixel output.

FIGS. 3A˜3G, cross sectional views taken along A-A′, B-B′, and C-C′lines of FIG. 2A, disclose a method for fabricating the pixel structureof the invention.

Referring to FIG. 3A, a first metal layer 11 is formed on a substrate12.

Referring to FIG. 3B, the first metal layer 11 is patterned to form ascan line 28 and a first data line 14 having at least one end 26 on thesubstrate 12. The scan line 28 extends in a first direction (as shown inFIG. 2A), and the first data line 14 extends in a second direction (asshown in FIG. 2A). The scan line 28 and the first data line 14 do notintersect with each other.

Referring to FIG. 3C, a first insulation layer 16 is formed on thesubstrate 12, overlying the scan line 28 and the first data line 14. Achannel layer 40 is then formed on the first insulation layer 16. Next,an ohmic contact layer 42 is formed on the channel layer 40. The channellayer 40 and the ohmic contact layer 42 constitute a semiconductorlayer. The semiconductor layer is then patterned to form a patternedsemiconductor layer 44.

Referring to FIG. 3D, a first opening 46 is formed to expose the end 26of the first data line 14.

Referring to FIG. 3E, a second metal layer (not shown) is formed on thefirst insulation layer 16 and the semiconductor layer 44. Next, thesecond metal layer is patterned to form a shielding electrode 18 and asecond data line 20 on the first insulation layer 16 and to form asource 32 and a drain 34 on the semiconductor layer 44. Thesemiconductor layer 44 contacts the source 32 and the drain 34 throughthe ohmic contact layer 42. The shielding electrode 18 overlaps thefirst data line 14. The second data line 20 is electrically connected tothe end 26 of the first data line 14 through the first opening 46.

Referring to FIG. 3F, a second insulation layer 22 is formed over theshielding electrode 18, the second data line 20, the source 32, and thedrain 34. A second opening 48 is then formed to expose the drain 34.

Referring to FIG. 3G, a pixel electrode 24 is formed on the secondinsulation layer 22. The pixel electrode 24 is electrically connected tothe drain 34 through the second opening 48 and overlaps the shieldingelectrode 18.

FIGS. 4A˜4F, cross sectional views taken along A-A′, B-B′, and C-C′lines of FIG. 2A, disclose a method for fabricating the pixel structureof the invention.

Referring to FIG. 4A, a first metal layer 11 is formed on a substrate12.

Referring to FIG. 4B, the first metal layer 11 is patterned to form ascan line 28 and a first data line 14 having at least one end 26 on thesubstrate 12. The scan line 28 extends in a first direction (as shown inFIG. 2A), and the first data line 14 extends in a second direction (asshown in FIG. 2A). The scan line 28 and the first data line 14 do notintersect with each other.

Referring to FIG. 4C, a first insulation layer 16 is formed on thesubstrate 12, overlying the scan line 28 and the first data line 14. Achannel layer 40 is then formed on the first insulation layer 16. Next,an ohmic contact layer 42 is formed on the channel layer 40. The channellayer 40 and the ohmic contact layer 42 constitute a semiconductor layer44′. A first opening 46 is then formed to expose the end 26 of the firstdata line 14.

Referring to FIG. 4D, a second metal layer (not shown) is formed on thesemiconductor layer 44′. Next, the second metal layer and thesemiconductor layer 44′ are defined by a half-tone or gray-tone mask toform a patterned semiconductor layer 44, a shielding electrode 18, asecond data line 20, a source 32 and a drain 34. The patternedsemiconductor layer 44 contacts the source 32 and the drain 34 throughthe ohmic contact layer 42. The shielding electrode 18 overlaps thefirst data line 14. The second data line 20 is electrically connected tothe end 26 of the first data line 14 through the first opening 46.

Compared to FIG. 3C, the patterned semiconductor layer 44 in FIG. 4D issimultaneously formed with the shielding electrode 18, the second dataline 20, the source 32, and the drain 34, that is, which are defined byone mask.

Referring to FIG. 4E, a second insulation layer 22 is formed over theshielding electrode 18, the second data line 20, the source 32, and thedrain 34. A second opening 48 is then formed to expose the drain 34.

Referring to FIG. 4F, a pixel electrode 24 is formed on the secondinsulation layer 22. The pixel electrode 24 is electrically connected tothe drain 34 through the second opening 48 and overlaps the shieldingelectrode 18.

The shielding electrode formed above the data line shields the electricfield produced from the data line. Additionally, a storage capacitor isformed between the shielding electrode and the pixel electrode, thuseffectively increasing the aperture ratio. Also, high storagecapacitance is obtained due to the decreased insulation layer.

While the invention has been described by way of example and in terms ofpreferred embodiment, it is to be understood that the invention is notlimited thereto. To the contrary, it is intended to cover variousmodifications and similar arrangements (as would be apparent to thoseskilled in the art). Therefore, the scope of the appended claims shouldbe accorded the broadest interpretation so as to encompass all suchmodifications and similar arrangements.

1. A pixel structure, comprising: a substrate; a first data line havingat least one end, disposed on the substrate; a first insulation layeroverlying the first data line and exposing a part of the end of thefirst data line; a shielding electrode disposed on the first insulationlayer and overlapped with the first data line; a second data line formedon the first insulation layer and electrically connected to the exposedend of the first data line; a second insulation layer overlying theshielding electrode and the second data line; and a pixel electrodeformed on the second insulation layer and overlapped with the shieldingelectrode.
 2. The pixel structure as claimed in claim 1, wherein theshielding electrode overlapping the first data line is located betweenthe pixel electrode and the first data line.
 3. The pixel structure asclaimed in claim 1, wherein the shielding electrode shields the electricfield produced from the first data line.
 4. The pixel structure asclaimed in claim 1, further comprising a storage capacitor formedbetween the shielding electrode and the pixel electrode.
 5. The pixelstructure as claimed in claim 1, further comprising a scan line formedon the substrate and intersecting the second data line.
 6. The pixelstructure as claimed in claim 5, wherein the scan line and the firstdata line are made of the same metal layer.
 7. The pixel structure asclaimed in claim 5, further comprising a thin film transistor having agate electrically connected to the scan line, a source electricallyconnected to the second data line, and a drain electrically connected tothe pixel electrode.
 8. The pixel structure as claimed in claim 7,wherein the shielding electrode, the second data line, the source, andthe drain are made of the same metal layer.
 9. The pixel structure asclaimed in claim 5, wherein the shielding electrode comprises a firstsub-shielding electrode extending along a first direction and across thefirst data line, and a second sub-shielding electrode extending along asecond direction and across the scan line.
 10. The pixel structure asclaimed in claim 9, wherein the shielding electrode is a network.
 11. Amethod for fabricating a pixel structure, comprising: providing asubstrate; forming a scan line and a first data line on the substrate,wherein the scan line is disposed along a first direction and the firstdata line is disposed along a second direction; forming a firstinsulation layer on the substrate, overlying the scan line and the firstdata line; forming a patterned semiconductor layer on the firstinsulation layer; forming a shielding electrode and a second data lineon the first insulation layer and forming a source and a drain on thepatterned semiconductor layer, wherein the shielding electrode isoverlapped with the first data line, and the second data line iselectrically connected to the end of the first data line; forming asecond insulation layer over the shielding electrode, the second dataline, the source, and the drain; forming an opening in the secondinsulation layer to expose the drain; and forming a pixel electrode onthe second insulation layer, wherein the pixel electrode is electricallyconnected to the drain through the opening and overlapped with theshielding electrode.
 12. The method as claimed in claim 11, furthercomprising forming another opening to expose the end of the first dataline such that the second data line is electrically connected to the endof the first data line through the another opening.
 13. The method asclaimed in claim 11, wherein the step of forming the scan line and thefirst data line comprises: forming a first metal layer on the substrate;and patterning the first metal layer to form the scan line and the firstdata line.
 14. The method as claimed in claim 11, wherein the step offorming the patterned semiconductor layer, the shielding electrode andthe second data line on the first insulation layer and the step offorming the source and the drain on the patterned semiconductor layercomprise: forming a semiconductor layer on the first insulation layer;forming a second metal layer on the semiconductor layer; and definingthe second metal layer and the semiconductor layer through a half-toneor gray-tone mask to form the patterned semiconductor layer, theshielding electrode, the second data line, the source, and the drain.15. The method as claimed in claim 11, wherein the step of forming thepatterned semiconductor layer comprises: forming a channel layer on thefirst insulation layer; forming an ohmic contact layer on the channellayer; and patterning the channel layer and the ohmic contact layer toform the patterned semiconductor layer.
 16. The method as claimed inclaim 15, wherein the ohmic contact layer is contacted with the sourceand the drain.
 17. A method for fabricating a pixel structure,comprising: providing a substrate; forming a first metal layer on thesubstrate; and patterning the first metal layer to form a scan line anda first data line, wherein the scan line is disposed along a firstdirection and the first data line is disposed along a second directionforming a first insulation layer on the substrate, overlying the scanline and the first data line; forming a patterned semiconductor layer onthe first insulation layer; forming a second metal layer and definingthe second metal layer to form a shielding electrode, a second dataline, a source and a drain, wherein the shielding electrode is disposedover the first insulation layer and overlapped with the first data line,the second data line is formed over the first insulation layer andelectrically connected to the end of the first data line, and the sourceand the drain are formed on the patterned semiconductor layer; forming asecond insulation layer on the shielding electrode, the second dataline, the source, the drain and the first insulation layer; forming anopening in the second insulation layer to expose the drain; and forminga pixel electrode on the second insulation layer, wherein the pixelelectrode is electrically connected to the drain through the opening andoverlapped with the shielding electrode.
 18. The method as claimed inclaim 17, further comprising forming another opening to expose the endof the first data line, such that the second data line is electricallyconnected to the end of the first data line through the another opening.19. The method as claimed in claim 17, wherein the patternedsemiconductor layer, the shielding electrode, the second data line, thesource and the drain are formed at the same time through a half-tonemask or a gray-tone mask.
 20. The method as claimed in claim 17, whereinthe step of forming the patterned semiconductor layer comprises: forminga channel layer on the first insulation layer; forming an ohmic contactlayer on the channel layer; and patterning the channel layer and theohmic contact layer to form the patterned semiconductor layer.